An important issue with integrated circuit (IC) design and manufacturing is protecting the on-chip components or devices from ESD. ESD is generally understood to refer to the sudden and momentary electric current that flows between two objects at different electrical potentials. In the electronics industry, the term describes momentary unwanted currents that may cause damage to electronic equipment. Examples of ESD events include sparks caused by static electricity, such as that which can be generated by walking on a rug or removing some types of plastic packaging, or through electrostatic induction, such as when a charged region on the surface of a Styrofoam cup or plastic bag induces potential on a nearby ESD sensitive component. While a spark causes only minor discomfort to people, it leads to severe damage to unprotected integrated circuits such as those made from semiconductor materials, e.g. silicon, and insulating materials such as silicon dioxide. Either of these materials can suffer permanent damage when subjected to the high voltages caused by an ESD event.
ESD protection can incorporated into IC device, where special circuit design techniques are used on the input and output pins of the device. A prior art embodiment widely adopted in the industry is depicted in FIG. 1. The IC device 10 includes an RF circuit 11 connected between a first voltage supply (VDD) pad 13 and a second voltage supply (VSS) pad 15. The RF circuit 11 has an input terminal at node 16 connected to signal pad 18. An ESD clamp circuit 14 is connected between supply pads 13 and 15 in parallel with an ESD block 12. ESD block 12 consists of a pair of bidirectional diodes labeled DP and DN in FIG. 1. Diode DP is connected between the VDD pad 13 and node 16, and the diode DN is coupled between the node 16 and the VSS pad 15.
The ESD protection built into the IC device 10 of FIG. 1 can provide protection against both positive and negative ESD events (positive beyond the power supply node voltage, and negative beyond the power supply return or ground voltage). However, with this design, there is a tradeoff between RF performance and ESD protection. The ESD protection circuit adds parasitic capacitances to the signal node 16. These capacitances decrease the bandwidth of the overall circuit. For sensitive designs, ESD circuits comprised of silicon controlled rectifiers (SCRs) and grounded gate re-channel MOSFETs (ggNMOSs) are used that may help to reduce the parasitic capacitance that is added to the signal node 16. However, high frequency RF and millimeter wave (mmW) applications, i.e. above 10 GHz, are more sensitive to any additional capacitance. As such, this traditional ESD circuit is not well suited for such applications.
Another example of an IC circuit 20 with ESD protection is shown in FIG. 2. The IC circuit 20 of FIG. 2 is identical to IC circuit 10 of FIG. 1 except for ESD block 22. ESD block 22 reduces the parasitic capacitance from the bidirectional diodes DP and DN of FIG. 1 by using a distributed architecture. The ESD block 22 has a plurality of sets of bidirectional diodes D1A to D4A and D1B to D4B as well as transmission lines TL1 to TL4 in the signal path between signal pad 18 and the input to the RF circuit 11. One major concern with this prior art configuration is that the transmission lines TL1 to TL4 are in the signal path from signal pad 18 to the RF circuit input, which leads to high insertion losses. Further, this architecture consumes a great deal of area, even in millimeter wave applications.
Yet another example of an IC circuit with integrated ESD protection is shown in U.S. Patent Publication No. 2008/0112101 A1 to McElwee et al., the entirety of which is hereby incorporated by reference herein. FIG. 3 shows an IC circuit 30 with the ESD protection approach of McElwee et al. McElwee et al. replaces the dual diode structure with an ESD block 32 having a transmission line TL1 coupled between the RF input node 36 and the ground node. The transmission line TL1 (also referred to as a shorted or short circuited stub or shorted shunt transmission line) acts as a filter. That is, the short stub has a high impedance at the operating frequency fRF of the RF circuit, so as to reduce its impact on circuit performance, and a low impedance within the expected ESD pulse spectrum. This configuration has an advantage over the prior art embodiment of FIG. 2 in that it allows desired signals from the signal pad 18 into the RF circuit 11 without significant insertion losses, while shunting unwanted signals from the signal pad 18, such as an ESD event, to ground. Yet improvements are still desired in ESD performance of such ESD devices.